SVE introduce new set of register
• 32 Z registers, z0, z1, . . . , z31;
Data register multiple of 128 bits up to 2048 bits, support 8-bit bytes, 16-bit halfwords, 32-bit words or 64-bit doublewords.
• 16 P registers, p0, p1, . . . , p15;
Predicate registers hold one bit for each byte available.
• 1 FFR register.
Special predicate register that differs from regular predicate registers by way of being used
implicitly by some dedicated instructions, called first faulting loads.
SVE is more flexible and efficient than the neon instruction . Target on the multi vector computation such as: machine learning and the graphic .
Ref:
1.A sneak peek into SVE and VLA programming
2.ARMv8-A SVE technology Hot Chips v12
3.The ARM Scalable Vector Extension
4.SIMD Programmingwith Larrabee
5.Using SVE intrinsics directly in your C code
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