Use DSP48 marco on Zedboard

1. add (*use_dsp48 ="yes"*) before module
can use before module wire and compute section but only useful in low bits design 

2.use  dsp 48 marco use like IP core can full customized by user

example : 48-bits and gate use dsp 48 slice

	module and48(A,B,C);
	input [47:0]A;
	input [47:0]B;
	output [47:0]C;
	// DSP48E1: 48-bit Multi-Functional Arithmetic Block
	// 7 Series
	// Xilinx HDL Libraries Guide, version 14.7
	DSP48E1 #(
	// Feature Control Attributes: Data Path Selection
	.A_INPUT("DIRECT"), // Selects A input source, "DIRECT" (A port) or "CASCADE" (ACIN port)
	.B_INPUT("DIRECT"), // Selects B input source, "DIRECT" (B port) or "CASCADE" (BCIN port)
	.USE_DPORT("FALSE"), // Select D port usage (TRUE or FALSE)
	.USE_MULT("MULTIPLY"), // Select multiplier usage ("MULTIPLY", "DYNAMIC", or "NONE")
	.USE_SIMD("ONE48"), // SIMD selection ("ONE48", "TWO24", "FOUR12")
	// Pattern Detector Attributes: Pattern Detection Configuration
	.AUTORESET_PATDET("NO_RESET"), // "NO_RESET", "RESET_MATCH", "RESET_NOT_MATCH"
	.MASK(48'h3fffffffffff), // 48-bit mask value for pattern detect (1=ignore)
	.PATTERN(48'h000000000000), // 48-bit pattern match for pattern detect
	.SEL_MASK("MASK"), // "C", "MASK", "ROUNDING_MODE1", "ROUNDING_MODE2"
	.SEL_PATTERN("PATTERN"), // Select pattern value ("PATTERN" or "C")
	.USE_PATTERN_DETECT("NO_PATDET"), // Enable pattern detect ("PATDET" or "NO_PATDET")
	// Register Control Attributes: Pipeline Register Configuration
	.ACASCREG(1), // Number of pipeline stages between A/ACIN and ACOUT (0, 1 or 2)
	.ADREG(1), // Number of pipeline stages for pre-adder (0 or 1)
	.ALUMODEREG(1), // Number of pipeline stages for ALUMODE (0 or 1)
	.AREG(1), // Number of pipeline stages for A (0, 1 or 2)
	.BCASCREG(1), // Number of pipeline stages between B/BCIN and BCOUT (0, 1 or 2)
	.BREG(1), // Number of pipeline stages for B (0, 1 or 2)
	.CARRYINREG(1), // Number of pipeline stages for CARRYIN (0 or 1)
	.CARRYINSELREG(1), // Number of pipeline stages for CARRYINSEL (0 or 1)
	.CREG(1), // Number of pipeline stages for C (0 or 1)
	.DREG(1), // Number of pipeline stages for D (0 or 1)
	.INMODEREG(1), // Number of pipeline stages for INMODE (0 or 1)
	.MREG(1), // Number of multiplier pipeline stages (0 or 1)
	.OPMODEREG(1), // Number of pipeline stages for OPMODE (0 or 1)
	.PREG(1) // Number of pipeline stages for P (0 or 1)
	)
	DSP48E1_inst (
	// Cascade: 30-bit (each) output: Cascade Ports
	.ACOUT(), // 30-bit output: A port cascade output
	.BCOUT(), // 18-bit output: B port cascade output
	.CARRYCASCOUT(), // 1-bit output: Cascade carry output
	.MULTSIGNOUT(), // 1-bit output: Multiplier sign cascade output
	.PCOUT(), // 48-bit output: Cascade output
	// Control: 1-bit (each) output: Control Inputs/Status Bits
	.OVERFLOW(), // 1-bit output: Overflow in add/acc output
	.PATTERNBDETECT(), // 1-bit output: Pattern bar detect output
	.PATTERNDETECT(), // 1-bit output: Pattern detect output
	.UNDERFLOW(), // 1-bit output: Underflow in add/acc output
	// Data: 4-bit (each) output: Data Ports
	.CARRYOUT(), // 4-bit output: Carry output
	.P(C[47:0]), // 48-bit output: Primary data output
	// Cascade: 30-bit (each) input: Cascade Ports
	.ACIN(), // 30-bit input: A cascade data input
	.BCIN(), // 18-bit input: B cascade input
	.CARRYCASCIN(), // 1-bit input: Cascade carry input
	.MULTSIGNIN(), // 1-bit input: Multiplier sign input
	.PCIN(), // 48-bit input: P cascade input
	// Control: 4-bit (each) input: Control Inputs/Status Bits
	.ALUMODE(4'b1100), // 4-bit input: ALU control input
	.CARRYINSEL(), // 3-bit input: Carry select input
	.CLK(), // 1-bit input: Clock input
	.INMODE(5'b00000), // 5-bit input: INMODE control input
	.OPMODE(7'b0110011), // 7-bit input: Operation mode input
	// Data: 30-bit (each) input: Data Ports
	.A(A[47:18]), // 30-bit input: A data input
	.B(A[17:0]), // 18-bit input: B data input
	.C(B[47:0]), // 48-bit input: C data input
	.CARRYIN(), // 1-bit input: Carry input signal
	.D(), // 25-bit input: D data input
	// Reset/Clock Enable: 1-bit (each) input: Reset/Clock Enable Inputs
	.CEA1(1'b0), // 1-bit input: Clock enable input for 1st stage AREG
	.CEA2(1'b0), // 1-bit input: Clock enable input for 2nd stage AREG
	.CEAD(1'b0), // 1-bit input: Clock enable input for ADREG
	.CEALUMODE(1'b0), // 1-bit input: Clock enable input for ALUMODE
	.CEB1(1'b0), // 1-bit input: Clock enable input for 1st stage BREG
	.CEB2(1'b0), // 1-bit input: Clock enable input for 2nd stage BREG
	.CEC(1'b0), // 1-bit input: Clock enable input for CREG
	.CECARRYIN(1'b0), // 1-bit input: Clock enable input for CARRYINREG
	.CECTRL(1'b0), // 1-bit input: Clock enable input for OPMODEREG and CARRYINSELREG
	.CED(1'b0), // 1-bit input: Clock enable input for DREG
	.CEINMODE(1'b0), // 1-bit input: Clock enable input for INMODEREG
	.CEM(1'b0), // 1-bit input: Clock enable input for MREG
	.CEP(1'b0), // 1-bit input: Clock enable input for PREG
	.RSTA(1'b0), // 1-bit input: Reset input for AREG
	.RSTALLCARRYIN(1'b0), // 1-bit input: Reset input for CARRYINREG
	.RSTALUMODE(1'b0), // 1-bit input: Reset input for ALUMODEREG
	.RSTB(1'b0), // 1-bit input: Reset input for BREG
	.RSTC(1'b0), // 1-bit input: Reset input for CREG
	.RSTCTRL(1'b0), // 1-bit input: Reset input for OPMODEREG and CARRYINSELREG
	.RSTD(1'b0), // 1-bit input: Reset input for DREG and ADREG
	.RSTINMODE(1'b0), // 1-bit input: Reset input for INMODEREG
	.RSTM(1'b0), // 1-bit input: Reset input for MREG
	.RSTP(1'b0) // 1-bit input: Reset input for PREG
	);
	endmodule

view raw gistfile1.txt hosted with ❤ by GitHub

ref
1.Dsp48 user guide

Zedboard cross compiler install

Install file

1.Open terminal -> chmod +x xilinx-2011.09-50-arm-xilinx-linux-gnueabi.bin -> sudo -s

2.Dpkg-reconfigure dash -> choose no

3./xilinx-2011.09-50-arm-xilinx-linux-gnueabi.bin

4.Export cross=/root/CodeSourcery/Sourcery_CodeBench_Lite_for_Xilinx_GNU_Linux/bin

5.$cross/arm-xilinx-linux-gnueabi-gcc file1.c -o file2.o

Learn GIT 1 - Install and push a commit

1.Git for Windows Install
 
2.Create a github accound and create a new repo

3.Open git bash -> git config --global user.email <mail>
               git config --global user.name <name>

4.Git remote add origin http:......

5.Create a folder  type git init -> git add file -> git commit -m <massage>

6.Git push origin //github name  master //localname

ref:
    1. Git 實務教學
    2. Learn Gin in 30 days